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data sheet clock fanout buffer/frequency divider 8V74S4622 8V74S4622 revision 1 05/11/15 1 ?2015 integrated device technology, inc. general description the 8V74S4622 is a versatile clock fanout buffer/frequency divider. the device supports the se lection, division and distribution of high-frequency clock signals with very low additive phase noise. the 8V74S4622 uses sige technology for an optimum of high clock frequency and low phase noise performance, combined with high power supply noise rejection and internal isolation. two selectable inputs are supported for differential and single ended clocks. each of the two outputs can select a copy or a frequency- divided input signal. the available frequency divisions are divide-by-2, 4, 5 and 8. both outputs support lvds interfaces. for each of the two outputs, a synchronous output enabled control is implemented for stopping the output clock synchronously to the input clock signal. all device configurations are through a logic pin interface. the device is packaged in a lead-free (rohs 6) 20-lead vfqfn package. the extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. the device is a member of the high-performance clock family from idt. features ? clock signal selection, frequency-division and distribution ? two outputs individually select: ? the input signal 2, 4, 5 and 8 or ? the input signal without frequency division (input signal is passed through) ? two inputs to support single-ended and differential operation ? differential input supports lvds and lvpecl signals ? single-ended input supports lvcmos signals ? two differential lvds outputs ? maximum input frequency (differential input clock): 2000mhz ? maximum output frequency: 2000mhz ? output skew: 22ps (maximum) ? additive phase noise rms, 125mhz, seln = 0, 12khz - 20mhz integration range: 180fs (maximum) ? lvds output rise/fall time: 260ps (maximum) ? 3.3v core and output supply voltages ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) 4x4 mm 2 20-lead vfqfn packaging block diagram n en 2 2 f clk en clk in nin vt refsel n[1:0] sel[1:0] noe0 noe1 2x 50 ? 0 1 0 1 0 1 q0 nq0 q1 nq1 pin assignment 20-pin, 4mm x 4mm vfqfn package 8V74S4622 v ddo1 q1 nq1 gnd noe0 v dd clk n1 n0 noe1 6 7 8910 20 19 18 17 16 sel0 gnd v ddo0 nq0 q0 refsel nin vt in sel1 2 3 4 5 1 15 14 13 12 11
8V74S4622 data sheet clock fanout buffer/frequency divider 2 revision 1 05/11/15 pin descriptions and characteristics 1 sel1 input pulldown function select control inpu t. lvcmos 3.3v interface. ? see table 3b for function. 2 in input differential clock signal non-inverting differential input. internal termination 50? . 3 vt differential clock input termination pin for built-in 50 ? termination interface. see th e application information for terminating lvds and lvpecl input signals. 4 nin input differential clock signal inverting differential input. ? internal termination 50 ? . 5 refsel input pulldown i nput select control input. lvcmos 3.3v interface. see table 3a for function. 6 v dd power positive supply voltage (3.3v). 7 clk input pulldown single-ended lvcmos 3.3v clock signal input. 8 n1 input pullup frequency divider control input. lvcmos 3.3v interface. ? see table 3c for function. 9 n0 input pulldown 10 noe1 input pullup output q1 enable control inpu t. lvcmos 3.3v interface. ? see table 3d for function. 11 v ddo1 power positive supply voltage (3.3v) for the q1 output. 12 q1 output differential clock output 1. lvds interface signals. 13 nq1 output 14 gnd power ground supply voltage (0v). connect to board gnd. 15 noe0 input pullup output q0 enable control inpu t. lvcmos 3.3v interface. ? see table 3d for function. 16 v ddo0 power positive supply voltage (3.3v) for the q0 output. 17 nq0 output differential clock output 0. lvds interface signals. 18 q0 output 19 gnd power ground supply voltage (0v). connect to board gnd. 20 sel0 input pulldown function select control inpu t. lvcmos 3.3v interface. ? see table 3b for function. ? gnd power exposed package ground supply voltage (gnd). connect to board gnd. table 1. pin descriptions 1 number name type description note: 1. pullup and pulldown refer to internal input resistors. see ta b l e 2 , pin characteristics, for typical values. table 2. pin characteristics symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pullup input pullup resistor 50 k ? r pulldown input pulldown resistor 50 k?
revision 1 05/11/15 3 clock fa nout buffer/frequency divider 8V74S4622 data sheet logic truth tables noex clk or in qx (f = f ) clk clk qx (f = f /5) figure 1. synchronous output enable timing diagram table 3a. input signal source select 1 note: 1. asynchronous control refsel input selection 0 (default) lvcmos input (clk) 1 differential input (in, nin) table 3b. function select 1 note: 1. asynchronous control. f clk is the selected input clock signal, n is the selected clock frequency divider. sel0 sel1 q0 q1 0 (default) 0 (default) f clk f clk 01f clk f clk n 10f clk n f clk 11f clk n f clk n table 3c. frequency divider n select 1 note: 1. asynchronous control. n1 n0 n divider 00 2 01 4 1 (default) 0 (default) 5 11 8 table 3d. output q0 and q1 enable 1 2 note: 1. individual setting for each output q0, q1. note: 2. synchronous to the clock signal to prevent runt pulses. ? see figure 1 noe0, noe1 q0, q1 state 0 enabled 1(default) disabled (output in logic low state) table 3e. synchronous output enable timing divider max. output enable/disable delay (in/ nin or clk to any output), measured in number of input clock pulses pass-through 1 2 4 4 7 5 9 8 16
8V74S4622 data sheet clock fanout buffer/frequency divider 4 revision 1 05/11/15 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of the product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating c onditions for extended periods may affect product reliability. dc electrical characteristics v dd positive supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd core power output ? supply current all outputs terminated with 100 ? betw een qx and nqx 37 43 ma i ddo output power supply current all outputs terminated with 100 ? betw een qx and nqx 73 83 ma table 4. absolute maximum ratings item rating supply voltage, v dd 4.6v inputs -0.5v to v dd + 0.5v outputs, i o (lvds) ? continuous current ? surge current 10ma ? 15ma input current in, nin 50ma v t current (i vt ) 100ma maximum junction temperature 125c storage temperature -65c to 125c esd - human body model 1 note: 1. according to jedec/jesd 22-a114/22-c101. 2000v esd - charged device model 1 500v table 5a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units table 5b. lvcmos/lvttl dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input ? high current clk, refsel, ? n0, sel0, sel1 v dd = v in = 3.465v 150 a n1, noe0, noe1 v dd = v in = 3.465v 5 a i il input ? low current clk, refsel, ? n0, sel0, sel1 v dd = 3.465v, v in = 0v -5 a n1, noe0, noe1 v dd = 3.465v, v in = 0v -150 a
revision 1 05/11/15 5 clock fa nout buffer/frequency divider 8V74S4622 data sheet table 5c. differential input dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units r in differential input resistance in, nin in to vt, nin to vt 50 : v cmr common mode input voltage. 1, 2 1v dd -v pp /2 v v pp input voltage swing 2 0.15 1.2 v v diff_in differential input voltage swing in, nin 0.30 v i in input current in, nin 30 ma note: 1. v cmr is defined as the signal crosspoint. note: 2. v il should not be less than -0.3v. v ih should not be greater than v dd. table 5d. lvds dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 460 mv ' v od v od magnitude change 50 mv v os offset voltage 1 1.4 v ' v os v os magnitude change 50 mv
f in input frequency in, nin 0 2000 mhz clk 0 250 mhz f out output frequency seln = 0 0 2000 mhz sel1 = 1, sel0 = 1 0 f in n mhz t pd propagation delay 2 , 3 seln = 0 (pass-through) 300 550 ps sel1 = 1 and se l0 = 1 n divider = 2, 4, 8 450 760 ps n divider = 5 550 900 ps t sk(o) output skew 4 , 5 22 ps t r / t f output rise/fall time q0, q1 20% to 80% 145 260 ps output ? isolation q0 to q1 and ? q1 to q0 f out = 125mhz and 25mhz 78 dbc input mux isolation f out = 125mhz 64 dbc t ji t(?) rms additive ph ase jitter (random) q0, q1 f out = 125mhz, integration range: 12khz - 20mhz, seln = 0 114 180 fs odc output ? duty cycle q0, q1 50% input duty cycle 45 55 % 8V74S4622 data sheet clock fanout buffer/frequency divider 6 revision 1 05/11/15 ac electrical characteristics table 6. ac characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c 1 note: 1. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater t han 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. symbol parameter test conditio ns minimum typic al maximum units note: 2. measured from v dd /2 of the input to the d ifferential output crosspoint. note: 3. measured from the differential input cro ssing point to the differential output crosspoint. note: 4. this parameter is defined in accordance with jedec standard 65. note: 5. defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential crosspoints.
revision 1 05/11/15 7 clock fa nout buffer/frequency divider 8V74S4622 data sheet parameter measurement information propagation delay output duty cycle/pulse width/period differential input level output skew t pd v dd 2 nqx qx nin in clk nq[0:1] q[0:1] nin in v dd gnd v cmr cross points v pp nqx qx nqy qy
8V74S4622 data sheet clock fanout buffer/frequency divider 8 revision 1 05/11/15 parameter measurement information output rise/fall time differential output voltage setup differential input voltage swing offset voltage 20% 80% 80% 20% t r t f v od nq[0:1] q[0:1] v pp v diff_in differenti a l volt a ge s wing = 2 x s ingle-ended v pp nin in o u t o u t lv d s dc inp u t ? s / s v dd
revision 1 05/11/15 9 clock fa nout buffer/frequency divider 8V74S4622 data sheet applications information differential input with built-in 50 : termination interface the in /nin with built-in 50 : terminations accept lvds, lvpecl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figure 2a to figure 2b to show interface examples for the in/nin input with built-in 50 : terminations driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination reco mmendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. in/nin input with built-in 50 : driven by an lvds driver figure 2b. in/nin input with built-in 50 : driven by an lvpecl driver recommendations for unused input and output pins inputs: clk input for applications not requiring the us e of a clock input, it can be left floating. though not required, but for additional protection, a 1k : resistor can be tied from the clk input to ground. in/nin inputs for applications not requiring the use of a differential input, a 1k : resistor should tie in to ground and a 1k : resistor should tie nin to v cc . lvcmos control pins all control pins have internal pull up or pulldown resistors; additional resistance is not required but can be added for additional protection. a 1k : resistor can be used. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 : across. if they are left floating, there should be no trace attached.
8V74S4622 data sheet clock fanout buffer/frequency divider 10 revision 1 05/11/15 vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead frame base package, amkor technology. figure 3. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
revision 1 05/11/15 11 clock fanout buffer/frequency divider 8V74S4622 data sheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission- line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devi ces with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 4a can be used with either type of output structure. figure 4b , which can also be used with both output types, is an optional termin a tion with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and conf irm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lv d s driver z o ? z t z t lv d s receiver figure 4a. lv d s driver z o ? z t lv d s receiver c z t 2 z t 2 standard lvds termination figure 4b. optional lvds termination
8V74S4622 data sheet clock fanout buffer/frequency divider 12 revision 1 05/11/15 power considerations this section provides information on power dissipation and juncti on temperature for the 8V74S4622 . equations and example calcul ations are also provided. the following calculation is for maximum current at 85c. 1. power dissipation. the total power dissipation for the 8V74S4622 is the sum of the core power plus the power dissipated due to the load. the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * i dd_max = 3.465v * 40.3ma = 139.6mw ? power (outputs) max = v ddo_max * i ddo _ max = 3.465v * 78ma = 270.3mw total power _max = 139.6mw + 270.3mw = 409.9mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = t ja * pd_total + t a tj = junction temperature t ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the app ropriate junction-to-ambient thermal resistance t ja must be used. assuming no air flow and a multi-layer board, the appr opriate value is 62.2c/w per ta b l e 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.41w * 62.2c/w = 110.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance t ja for 20-lead vfqfn, forced convection t ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 62.2c/w 54.4c/w 48.8c/w
revision 1 05/11/15 13 clock fanout buffer/frequency divider 8V74S4622 data sheet reliability information table 8. t ja vs. air flow table for a 20-lead vfqfn transistor count the transistor count for 8V74S4622 is: 1723 t ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 62.2c/w 54.4c/w 48.8c/w
8V74S4622 data sheet clock fanout buffer/frequency divider 14 revision 1 05/11/15 20-lead vfqfn package outline a nd package dimensions
revision 1 05/11/15 15 clock fanout buffer/frequency divider 8V74S4622 data sheet ordering information 8V74S4622nlgi 8V74S4622nlgi 20-lead vfqfn, lead-free tray -40c to 85c 8V74S4622nlgi8 8V74S4622nlgi 20-lead vfqfn, lead-free tape & reel -40c to 85c 8V74S4622nlgi/w 8V74S4622nlgi 20-lead vfqfn, lead-free tape & reel, pin 1 or ientation eia-481-d -40 ? c to 85 ?c table 10. pin 1 orientation in tape and reel packaging table 9. ordering information part/order number marking package shipping packaging temperature part number suffix pin 1 orientation illustration 8 quadrant 1 (eia-481-c) /w quadrant 2 (eia-481-d)
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